DACs have a wide range of uses, some of which impose particular performance requirements. For example, DACs are often used in feedback systems having one or more loops with series arrangements of analog and digital devices, requiring respective DACs and analog-to-digital converters (ADC)s. For purposes of this description “analog” means continuous-time and continuous-valued, and “digital” means discrete-time and discrete-valued.
One typical example of such a system samples an analog system state (e.g., the system output) with an N-bit analog-to-digital converter (ADC), compares the digital state sample with a digital reference data, and generates a digital error data. A digital control processor may transform the digital error data through a feedback function to generate an M-bit system control data, where N may be equal to M. An M-bit DAC converts the digital control input data into an analog control signal and inputs this to the system.
The digital control processor generates the M-bit system control data with a value urging the system state in a direction opposite the direction of the error, so as to reduce the error. If the feedback loop is properly designed, and the devices forming the loop are functioning properly, the iterations of error detection, control data calculation, and inputting the control data to the system to urge the system state in a direction reducing the magnitude of the error will cause the system to eventually reach the reference state, regardless of the location of the reference state within the allowable domain of reference states, and regardless of the system's initial state. However, if the loop is not properly designed, or if certain components in the loop have certain kinds of non-ideal operation, the system may, for example, enter a periodic oscillation of over-correcting to be above and then below the reference point.
Selection of a DAC for use in a feedback loop is undertaken in view of the system criteria listed above. DAC parameters bearing on such selection include bit resolution, conversion speed, settling time (which is related to conversion speed), and monotonicity.
The DAC bit resolution establishes, in part, an upper bound on the accuracy to which the system can match the reference signal. The monotonicity establishes, or affects, the system's ability converge, or “lock” to the reference signal, as well as affecting transient behavior of the system in moving from an initial state to, or toward, the reference state. Other selection factors include, for example, cost, power budget, and area and volume budget.
There are three known general DAC architectures for selecting among, and each has known benefits or advantages, as well as drawbacks or limitations, pertaining to its use as a feedback DAC.
One such DAC architecture is the binary weighted M-bit DAC. A binary M-bit DAC consists generally of one voltage-to-current source for each of the M input bits, each of the sources exponentially weighted according to the bit position. A four-bit binary weighted DAC, for example, consists of four weighted current sources; an LSB source that converts a “1” to 20, i.e., one LSB unit of current; a next higher bit source that converts a “1” to 21 or two LSB units of current, continuing to an MSB bit source, that converts a “1” to 23 or eight LSB units of current.
The advantage of the binary weighted DAC is a low parts count, because it needs only one current source for each of the M input bits.
The binary weighted M-bit DAC, however, has a strict accuracy requirement for its M current sources, and this gets exponentially (base 2) higher with a linear increase in M. If the accuracy is not met, the result may be a non-monotonic DAC operation, namely there may be instances where certain increases in value of the M-bit digital input result not in an increase in DAC output current but, instead, a decrease. A DAC having such behavior may, if part of feedback loop, cause the system enter a continuous oscillation, or “hunting,” about a reference point, because of over-correcting or missing state values.
The strictness of the accuracy requirement will be illustrated by example. Assume a four-bit binary weighted DAC having an ideal LSB current source, generating one LSB unit of current for an LSB value of “1.” Assume that the example has the following inaccuracies: an MSB current source that is ¾ of an LSB current too low, a second-to-MSB current source that is ½ of an LSB current too high, and a third-to-MSB current source that is ¼ of an LSB current too high. If the input is “0111” the resulting DAC output current will be ¾ of an LSB too high, i.e., a current value of decimal 7¾ M instead of decimal 7, due to the above-described inaccuracy of the MSB-1 and MSB-2 sources. If the input value increases by one LSB to change to “1000,” though, the output changes not to decimal 8 units of current, but to decimal 7¼ because of the above-described example inaccuracy of ¾ LSB in the MSB current source. Therefore, in this example, an increase of one LSB in the binary input causes a decrease in the DAC output, from decimal 7¾ to decimal 7¼, instead of an increase in the DAC output current.
Another architecture of DAC, termed a “thermometer DAC,” forms an M-bit DAC using a stack of 2M−1 equal value current sources, connected in parallel and connected through an ON-OFF switch to a current summing device. An M to 2M−1 line binary decoder converts an M-bit binary input into 2M−1 control lines, each connected one of the 2M−1 ON-OFF switches. As an illustrative example, a four-bit thermometer DAC has fifteen (15) current sources with ON-OFF switches (16 sources if an overflow is included). If the M-bit binary input is “0111,” representing decimal “7,” the binary decoder generates a corresponding seven of the control lines as ON, typically switching on only the bottom seven of the 2M−1 one-bit current sources. If the M-bit input is increased by one LSB to represent a decimal “8” the binary decoder generates one additional of the 2M−1 control lines as ON, adding one LSB of current to the output. Hence, the name “thermometer” DAC.
The thermometer DAC is particularly useful in a feedback arrangement because it is inherently monotonic. Stated differently, for all values throughout the range of the M-bit input, an increase (or decrease) of the input value by one least significant bit (LSB) connects (or removes) exactly one of the thermometer's current sources. Therefore, regardless of the relative accuracy of the particular current source added (or removed), there is an increase (or decrease) in the DAC output current.
A thermometer DAC, however, has a high parts count, essentially doubling for each increase of one bit. As an illustrative example, a 10-bit thermometer DAC requires decimal 1023 current source elements. Increasing the resolution to 14 bits requires four times the quantity of current source elements, namely decimal 4196. For each added bit the doubling continues such that, for a 16-bit thermometer DAC, approximately 64 thousand (64K) switched current sources are required. This parts count makes a thermometer DAC impractical for some applications.
There is a third known general type of DAC, though, termed a “segmented DAC,” that obtains some, but not all of the monotonicity benefit of the thermometer DAC, while avoiding some, but not all of the monotonicity shortcomings of the binary weighted DAC.
A conventional M-bit segmented DAC consists of multiple DACs, typically two, each receiving a block of the M bits. One example of a conventional M-bit segmented DAC breaks the M bits into two segments—an H-bit upper segment and an L-bit lower segment. The H-bit upper segment then feeds a high level DAC (H-DAC) and the L-bit lower segment feeds a low level DAC (L-DAC), each generating a current corresponding to the sum of the binary weights, within the M-bit input, of all of the non-zero bits in the segment that it receives.
As readily seen, in accordance with its principle of operation, the full range of the L-DAC within a conventional segmented M-bit DAC spans, ideally, exactly one LSB of the H-DAC, such that the L bits establish 2L binary levels in the span. Since the H-DAC provides 2H incremental levels, and the L-DAC provides 2L levels between each of the H-DAC levels, the total resolution is 2H×2L=2H+L=2M.
The known benefit of the conventional segmented DAC is that, since each of the DACs has a smaller number of bits than M, each may be implemented as a thermometer DAC. This can be demonstrated by picking an example M of sixteen bits, and implementing it as a conventional two-segment DAC, using an eight bit H-DAC and an eight-bit L-DAC. Both the H-DAC and the L-DAC require 28−1=255 current sources. A 255 level thermometer DAC is readily manufacturable and requires a relatively small die size. Therefore, since both the H-DAC and the L-DAC can be implemented as a thermometer DAC, each is inherently monotonic. Further, the total number of current sources is only 512. For purposes of comparison, if the sixteen-bit DAC were constructed as one thermometer DAC the number of current sources would be 216−1, which is approximately 64 thousand or 64K. The conventional two segment implementation of a sixteen bit DAC therefore requires 510/64,000 or 0.7% of the number of devices as a sixteen bit thermometer DAC.
A long known issue of the conventional segmented DAC, though, arises from its fundamental principle, which is that it obtains its reduction in parts count by substantially the same principle that is exploited by the weighted binary DAC, except that instead of implementing each bit of the M bits as a weighted current source, the M bits are broken into blocks, and each block is implemented as a weighted current source. Therefore, for all DACs corresponding to any block above the least significant block, the change in its output current corresponding to a one LSB change in its input bits, must match the total full scale (all 1s) output of all DACs corresponding to bit blocks having smaller weight than that block—to within one LSB current.
For example, in a conventional two-segment. DAC, the change in current output from the H-DAC in response to a one LSB change in its input must match the full scale current of the L-DAC within one LSB of the L-DAC, for every bit combination input to the H-DAC. Therefore, if both the H-DAC and the L-DAC are eight (8) bits, and a one LSB current step from the L-DAC is labeled “q,” each one bit change in the H-DAC input must change the H-DAC output by 256q, plus or minus q. If the change is 255q then, assuming the L-DAC is perfect, there will be no change in the DAC output in response to a one. If such matching is not maintained, the segmented DAC may exhibit a non-monotonicity at the bit value transition points where the L-DAC input rolls over, i.e., goes from all “1s” to all “0s,” thereby incrementing (or decrementing) the LSB of the H-DAC by one bit. This is inherent to the segmented DAC architecture.
FIGS. 1-3 illustrate the above-described non-monotonicity of known segmented DACs, as it manifests in a simulated input-output characteristic of a conventional segmented sixteen (16) bit DAC, formed of an eight (8)-bit H-DAC (not shown in the figures) and an eight (8)-bit L-DAC (not shown in the figures). The FIG. 1-3 simulation spans several consecutive LSBs of the H-DAC. FIG. 1 shows a first case, where all four of the illustrated LSB increments of the H-DAC labeled 12A, 12B, 12C and 12D, are the same height, each matching the full range of the L-DAC, labeled L-RANGE, within an accuracy of one LSB of the L-DAC. FIG. 2 shows a second case, where the LSB increment 12B′ of the H-DAC output resulting from its binary input going from hexadecimal “10,” i.e., binary “1010,” to hexadecimal “11,” i.e., binary “1011,” is smaller than the L-RANGE of the L-DAC by an amount more than one LSB of the L-DAC. FIG. 3 shows a third case, where the LSB increment 12B″ of the H-DAC output, at the same location as the 12B′ increment of FIG. 2, is larger than the L-RANGE of the L-DAC, by an amount more than one LSB of the L-DAC.
Referring now to FIG. 1, if the current represented by one LSB of the 16-bit input is “q,” the LSB of the HDAC will be 256q, and the range of the whole segmented DAC will be 65536q. As shown, when the digital input is hexadecimal “1000” the H-DAC DAC output is analog “4096” of q units of current, while the L-DAC current is zero. When the input varies from hexadecimal “10FF,” hereinafter “10FF H” to “1100 H,” the input to the H-DAC increases by one H-DAC LSB to “11,” while the input to the L-DAC rolls over to “00.” Since the FIG. 1 H-DAC has LSBs matched to the L-DAC, the result is that the output of the H-DAC increases by 256q, while the current of the L-DAC decreases by 255q. This yields a net increase in the segmented DAC output of q, representing a one LSB increase in the 16-bit input. This is shown by the near abutting ends (spaced by one current unit q) of the L-DAC range at position 14 and at the position after input goes from “10FF H” to “1100 H.”
However, for various reasons it is often substantially impossible, at least within typical constraints of a manufactured product, for the LSB of an H-DAC to exactly equal to the whole range of the L-DAC. Therefore, even if both of the sub-DACs (i.e., the H-DAC & L-DAC) are monotonic, which is provided by thermometer DACs, the DAC as a whole will not be monotonic over its entire range.
FIG. 2 illustrates a simulated input-output characteristic of the same standard segmented sixteen (16)-bit DAC shown as simulated in FIG. 1, showing an example of a second case type scenario, where span 12b′ between consecutive LSBs “10 H” and “11 H” of the H-DAC, which should have analog values spaced 256q apart, are instead smaller, by more than q, than 256q, i.e., the full range of the L-DAC. As can be seen, since the current increase from the one H-DAC LSB going from “10 H” to “11 H” is substantially less than 256q, that one LSB of the H-DAC input is substantially less than the subtraction of 255q resulting from the roll-over of the L-DAC input all “00.” As a result, the overall output of the H-DAC will decrease by the amount labeled SEGMENT ERROR, instead of increase, in response to the input going from “10FF H” to “1100 H”. As is well known to persons of ordinary skill in the art, such non-monotonicity of a DAC within certain feedback loops such as, for example, a frequency-lock loop digital controlled oscillator (not shown in FIG. 2) may cause the system oscillate around these segment points, i.e., each one-LSB increase (or decrease) of the H-DAC.
FIG. 3 illustrates a simulated input-output characteristic of the same standard segmented sixteen (16)-bit DAC as simulated for FIGS. 1 and 2, showing an example of a third case type scenario, where the LSB 14′ of the H-DAC representing the current increase from the H-DAC input going from “10 H” to “11 H” is substantially more than 256q, that one LSB of the H-DAC input is substantially more than the subtraction of 255q resulting from the roll-over of the L-DAC input all “00.” As a result, the overall output of the H-DAC will increase not by q, but by a substantially larger by the amount labeled SEGMENT SKIP ERROR. This means the output range in the SEGMENT SKIP ERROR is lost and cannot be accessed. Therefore, DAC accuracy is lost and, further, states of the controlled system such as, for example, an output frequency of a FLL will be lost as well.